With the advent of Surface Mount Devices, Application Specific ICs (ASICs), and double sided boards, board level testing is rapidly becoming a major problem. The test cost also increases dramatically with higher density.
One technique employed in IC designs to improve testability and reduce test cost, is to partition off sections of the main logic design into separately testable modules. The partitioning is accomplished by surrounding the modules with a boundary scan ring, using either Shift Register Latches (SRL) or Scan Registers (SR). This same technique can be used at the boundary of any well-defined logic block. Utilizing a boundary scan technique around an IC's I/O structure provides similar benefits at the board level as at the IC level.
Traditionally in systems employing the boundary scan technique, a trade-off had to be made between the length of the scan and the number of connectors required to interface with the SRLs. If the minimum number of connectors was used (i.e. only that needed to scan in/out the test data/result), then the length of the scan could be tremendous. Regardless of how few points were to be tested, the scan length would not change. Alternatively, the scan length could be broken into smaller segments, but the access lines (connectors) would increase proportionally.
Due to the fixed scan length limitations, it has been impractical to consider adding boundary scan tests internal to an IC where logic blocks may be tested, in conjunction with a system level test (i.e. multi-ICs). This has resulted in having to have a separate testing method for an IC and a board or system.
The present invention allows a continuous scan path to be compressed or expanded so that the path only passes thru the logic sections being tested. This Fast Scan (FSCAN) technique is implemented with a simple logic design that is referred to as the Device Select Module (DSM).
By using FSCAN, devices that are connected on a serial data ring can be selected or deselected allowing the serial path to either flow throw or bypass the device's internal scan path. In addition, FSCAN can be used in IC designs to partition off sections of the core logic for internal scan testing. One advantage of FSCAN over the traditional scan path is that it reduces the test time required to load and unload the scan path and eliminates the need of additional IC pins and board I/O connectors for individual device scan-enable control signals.
Another advantage of the FSCAN technique is that it tends to make the scan path more fault tolerant. For example if a scan sub-ring connected to the main scan path were to experience a short or open condition, causing it to disable the rest of the scan path, it could simply be deselected using the FSCAN's Device Select Module (DSM). Once a DSM is deselected, the main scan path simply bypasses that sub-ring.
It is an object of the present invention to minimize the number of connectors needed for testing.
It is also an object of the present invention to allow boundary scan testing to be performed on a portion of an individual device, an individual device as a whole, a group of devices, and a system.
It is a further object of the present invention to allow a variable scan length so as to minimize scan times.
It is an additional object of the present invention to create a higher degree of fault tolerance.
These and other objects are achieved by a boundary scan test system comprising:
a plurality of logic devices, each having input and output lines for selectively transmitting and receiving data;
a first and second of said logic devices, each further including a logic core and a scan cell having multiple bit positions;
said scan cells being logically located between said logic core and said input and output lines of said first and second logic devices wherein selected bits of said multiple bit positions, under control, are selectively substituted for said data;
each of said first and second said logic devices further including a device select module connected to respective said scan cells of said first and second said logic devices;
said device select module of said first logic device being also coupled to a first bus for receiving test data bits and being further coupled to said device select module of said second logic device via a second bus;
said device select module of said first logic device, in response to selected ones of said test data bits, selectively loading other selected ones of said test data bits into said scan cell connected to said device select module of said first logic device and transmitting other selected ones of said test data bits to said device select module of said second logic device via said second bus; and
said device select modules further controlling the said substitution of data by said connected scan cells.